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19-1557; Rev 0; 10/99
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
General Description
The MAX5100 parallel-input, voltage-output, quad 8-bit digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 20-pin TSSOP package. Internal precision buffers swing Rail-to-Rail (R) , and the reference input range includes both ground and the positive rail. All four DACs share a common reference input. The MAX5100 provides double-buffered logic inputs: four 8-bit buffer registers followed by four 8-bit DAC registers. This keeps the DAC outputs from changing during the write operation. An asynchronous control pin, LDAC, allows for simultaneous updating of the DAC registers. The MAX5100 features a shutdown mode that reduces current to 1nA, as well as a power-on reset mode that resets all registers to code 00 hex on power-up. o Ultra-Low Supply Current 0.4mA while Operating 1nA in Shutdown Mode o Ultra-Small 20-Pin TSSOP Package o Ground to VDD Reference Input Range o Output Buffer Amplifiers Swing Rail-to-Rail o Double-Buffered Registers for Synchronous Updating o Power-On Reset Sets All Registers to Zero
Features
o +2.7V to +5.5V Single-Supply Operation
MAX5100
Ordering Information
PART MAX5100AEUP MAX5100BEUP TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP 20 TSSOP INL (LSB) 1 2
Applications
Digital Gain and Offset Adjustments Programmable Attenuators Portable Instruments Power-Amp Bias Control
TOP VIEW
OUTB 1 OUTA 2 VDD 3 REF 4 SHDN 5 WR 6 D7 7 D6 8 D5 9 D4 10 20 OUTC 19 OUTD 18 GND 17 A0
Pin Configuration
MAX5100
16 A1 15 LDAC 14 D0 13 D1 12 D2 11 D3
TSSOP
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V D_, A_, WR, SHDN, LDAC to GND...........................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 7.0mW/C above +70C) .......559mW Operating Temperature Range MAX5100_EUP ..............................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VREF = +2.7V to +5.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code-Error Supply Rejection Zero-Code Temperature Coefficient Gain Error (Note 2) Gain-Error Temperature Coefficient INL DNL ZCE MAX5100A MAX5100B Guaranteed monotonic Code = 00 hex Code = 00 hex, VDD = 2.7V to 5.5V Code = 00 hex Code = F0 hex Code = F0 hex VDD = 2.7V to 3.6V, VREF = 2.5V VDD = 4.5V to 5.5V, VREF = 4.096V REFERENCE INPUT Input Voltage Range Input Resistance Input Capacitance DAC OUTPUTS Output Voltage Range DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance 2 VIH VIL IIN CIN VIN = VDD or GND 10 RL = VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 2 3 0.8 1.0 0 320 460 15 VREF VDD 600 V k pF V 0.001 1 LSB 1 10 1 8 1 2 1 20 10 Bits LSB LSB mV mV V/C % LSB/C SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Rejection
Code = FF hex
V V A pF
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREF = +2.7V to +5.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Output Voltage Slew Rate Output Settling Time (Note 3) Channel-to-Channel Isolation (Note 4) Digital Feedthrough (Note 5) Digital-to-Analog Glitch Impulse From code 00 to code F0 hex To 1/2LSB, from code 10 to code F0 hex Code 00 to code FF hex Code 00 to code FF hex Code 80 hex to code 7F hex REF = 2.5Vp-p at 1kHz REF = 2.5Vp-p at 10kHz 0.6 6 500 0.5 90 70 dB 60 650 60 tSDR tSDN VDD IDD To 1/2LSB of final value of VOUT IDD < 5A 2.7 370 0.001 tAS tAH tDS tDH tWR tLD 5 0 25 0 20 20 13 20 5.5 700 1 kHz VRMS s s V A A ns ns ns ns ns ns V/s s nVs nVs nVs SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5100
Signal-to-Noise plus Distortion Ratio
SINAD
VREF(DC) = 1.5V, VDD = 3V, code = FF hex
Multiplying Bandwidth Wideband Amplifier Noise Shutdown Recovery Time Time to Shutdown POWER SUPPLIES Power-Supply Voltage Supply Current (Note 6) Shutdown Current DIGITAL TIMING (Figure 1) (Note 7) Address to WR Setup Address to WR Hold Data to WR Setup Data to WR Hold WR Pulse Width LDAC Pulse Width (Note 8)
REF = 0.5Vp-p, VREF(DC) = 1.5V, VDD = 3V, -3dB bandwidth
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded. Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex, and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF * 240 / 256). Note 3: Output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of VOUT's final value. Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any other DAC output. The measured channel has a fixed code of 80 hex. Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight data inputs with WR at VDD. Note 6: RL = , digital inputs at GND or VDD. Note 7: Timing measurement reference level is (VIH + VIL) / 2. Note 8: If LDAC is activated prior to WR's rising edge, it must stay low for tLD (or longer) after WR goes high.
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100
ADDRESS tAS WR ADDRESS VALID tWR tAH-
tLD LDAC (NOTE 8)
tDSDATA DATA VALID
tDH-
Figure 1. Timing Diagram
Typical Operating Characteristics
(VDD = VREF = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE vs. SINK CURRENT
MAX5100 toc01
DAC FULL-SCALE OUTPUT VOLTAGE vs. SOURCE CURRENT
MAX5100 toc02
SUPPLY CURRENT vs. TEMPERATURE
320 SUPPLY CURRENT (A) 300 280 260 240 220 VDD = 3V; CODE = F0 HEX VDD = 5V; CODE = 00 HEX 1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (RL = ) VDD = 5V; CODE = F0 HEX
MAX5100 toc03 MAX5100 toc06
1.2 1.0 0.8 VOUT (V) 0.6 0.4 0.2 0 0 2 4 6 8 VDD = VREF = 5V
6 5 4 VOUT (V)
340
VDD = VREF = 3V
VDD = VREF = 5V VDD = VREF = 3V
3 2 1 0
VDD = 3V; CODE = 00 HEX
200 180 0 2 4 6 8 10 -40 -20 0 20 40 60 80 100 SOURCE CURRENT (mA) TEMPERATURE (C)
10
SINK CURRENT (mA)
SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = 3V)
MAX5100 toc04
SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = 5V)
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (RL = ) CODE = F0
MAX5100 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
0 -10 -20 VDD = +3V DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 80kHz FILTER
300 280
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (RL = ) CODE = F0
320 300 SUPPLY CURRENT (A) 280 260 240 220
SUPPLY CURRENT (A)
260 240 220 200 180 160 140 0 0.5 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) CODE = 00
THD + NOISE (dB)
-30 -40 20kHz REF SIGNAL -50 -60 -70 10kHz REF SIGNAL
CODE = 00
200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
1kHz REF SIGNAL -80 0 0.5 1.0 1.5 2.0 2.5 REFERENCE AMPLITUDE (Vp-p)
4
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
Typical Operating Characteristics (continued)
(VDD = VREF = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
MAX5100
TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
-10 -20 THD + NOISE (dB) -30 -40 -50 -60 -70 -80 1 10 FREQUENCY (kHz) 100 REF = 2Vp-p REF = 0.5Vp-p VDD = +3V DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 1kHz FREQUENCY 500kHz FILTER
MAX5100 toc07
REFERENCE INPUT FREQUENCY RESPONSE
MAX5100 toc08
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
CH1 = LDAC, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED DAC CODE FROM 80 TO 7F HEX 1
MAX55100 toc09 MAX5100 toc15 MAX55100 toc12
0
10 0 -10 OUTPUT AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80 -90 CODE = FF HEX, REF IS 1Vp-p SIGNAL VREF = 1.5V 0.01 0.1 1
REF = 1Vp-p
2
10
1s/div
FREQUENCY (MHz)
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
MAX55100 toc10
DIGITAL FEEDTHROUGH GLITCH IMPULSE (0 TO 1 DIGITAL TRANSITION)
CH1 = D7, 2V/div CH2 = VOUTA, 2mV/div, AC-COUPLED 0 TO 1 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH, LDAC LOW)
MAX55100 toc11
DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSITION)
CH1 = D7, 2V/div CH2 = VOUTA, 2mV/div, AC-COUPLED 1 TO 0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH, LDAC LOW)
CH1 = LDAC, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED DAC CODE FROM 7F TO 80 HEX 1
2
1 2
1 2
1s/div
20ns/div
20ns/div
POSITIVE SETTLING TIME
MAX55100 toc13
NEGATIVE SETTLING TIME
MAX55100 toc14
INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
0.5 0.4 0.3 0.2 INL/DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 INL DNL RL =
CH1 = WR, 2V/div CH2 = VOUTA, 2V/div DAC CODE FROM 10 TO F0 HEX 1
CH1 = WR, 2V/div CH2 = VOUTA, 2V/div DAC CODE FROM 10 TO F0 HEX 1
2
2
1s/div
1s/div
0
32
64
96
128 160 192 224 256
DIGITAL CODE
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100
Pin Description
PIN 1 2 3 4 5 6 7-14 15 16 17 18 19 20 NAME OUTB OUTA VDD REF SHDN WR D7-D0 LDAC A1 A0 GND OUTD OUTC DAC B Voltage Output DAC A Voltage Output Positive Supply Voltage. Bypass VDD to GND using a 0.1F capacitor. Reference Voltage Input Shutdown. Connect SHDN to GND for normal operation. Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1. Data Inputs 7-0 Load DAC Input (active low). Drive the asynchronous LDAC input low to transfer the contents of all input latches to their respective DAC latch. DAC Address Select Bit (MSB) DAC Address Select Bit (LSB) Ground DAC D Voltage Output DAC C Voltage Output FUNCTION
Detailed Description
Digital-to-Analog Section
The MAX5100 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the applied reference voltage input. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. The device can be used in multiplying applications. The voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output. The functional block diagram for the MAX5100 is shown in Figure 2.
device out of shutdown, allow 13s for the output to stabilize.
Output Buffer Amplifiers
The DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/s. The typical settling time to 1/2LSB at the output is 6s when loaded with 10k in parallel with 100pF.
Reference Input
The MAX5100 provides a code-independent input impedance on the REF input. The input impedance is typically 460k in parallel with 15pF, and the reference input voltage range is 0 to VDD. The reference input accepts positive DC signals as well as AC signals with peak values between 0 and VDD. The voltage at REF sets the full-scale output voltage for the DAC. The output voltage (VOUT) for any DAC is represented by a digitally programmable voltage source as follows: VOUT = (NB * VREF) / 256 where NB is the numeric value of the DAC binary input code.
Low-Power Shutdown Mode
The MAX5100 features a shutdown mode that reduces current consumption to 1nA. A high voltage on the shutdown pin shuts down the DACs and the output amplifiers. In shutdown mode, the output amplifiers enter a high-impedance state. When bringing the
6
Digital Inputs and Interface Logic
In the MAX5100, address lines A0 and A1 select the DAC that receives data from D0-D7, as shown in Table 1.
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100
INPUT LATCH A DAC A LATCH
DAC A
OUTA
INPUT LATCH B D0-D7 INPUT LATCH C
DAC B LATCH
DAC B
OUTB
DAC C LATCH
DAC C
OUTC
INPUT LATCH D AO A1 CONTROL LOGIC
DAC D LATCH
DAC D
OUTD
MAX5100 LDAC REF SHDN
WR
Figure 2. Functional Diagram
Table 1. MAX5100 Address Table (Partial)
LDAC H H L WR H L H A1 X L X A0 X L X LATCH STATE Input and DAC data latched DAC A input latch transparent All 4 DACs' DAC latches transparent DAC A input registers transparent and all 4 DACs' DAC latches transparent DAC B input latch transparent DAC C input latch transparent DAC D input latch transparent
Applications Information
External Reference
The reference source resistance must be considerably less than the reference input resistance. To keep within 1LSB error in an 8-bit system, RS must be less than RREF / 256. Hence, maintain a value of RS <1k to ensure 8-bit accuracy. If VREF is DC only, bypass REF to GND with a 0.1F capacitor. Values greater than this improve noise rejection.
L H H H
L L L L
L L H H
L H L H
Power Sequencing
The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings.
H = High state, L = Low state, X = Don't care
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1F capacitor, located as close to VDD and GND as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
When WR is low, the addressed DAC's input latch is transparent. Data is latched when WR is high. The MAX5100 LDAC feature allows simultaneous updating of all four DACs. LDAC low latches the data in the data registers to the DAC registers. If simultaneous updating is not required, tie LDAC low to keep the DAC latches transparent. If WR and LDAC are low simultaneously, avoid output glitches by ensuring that data is valid before the two signals go low. When the device powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex.
Chip Information
TRANSISTOR COUNT: 6848
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+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100
Package Information
TSSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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